A circuit simulation tool may be used to determine a delay to logic transitions on one or more outputs of a proposed circuit design based on a delay from logic transitions on one or more inputs of the proposed circuit design. For example, a circuit simulation tool may determine a delay to logic transitions on one or more outputs of each component (e.g., logic device) included in the circuit design based on a delay from logic transitions on one or more inputs of the component. Thereby, the overall response of the circuit may be determined.
For complicated circuit designs, simulation of the exact behavior of each component within a circuit may be time consuming and in some cases prohibitive. Accordingly, static timing tools which model the timing behavior of a circuit and/or each component included in the circuit rather than the overall response of each circuit component have been developed. For example, static timing tools may be used to determine when one or more signals should be inputted by a portion of a circuit design, when one or more signals will be outputted from a portion of the circuit design, or other timing behavior of the circuit design.
An important aspect of successfully supporting circuit design using a static timing tool is accurately modeling the timing behavior of a latch, such as a master/slave latch. In many circuit designs, latches are used to divide logic included in a circuit design into paths of equal length which are bounded by the latches. Accordingly, any static timing model of such a circuit should accurately model the timing behavior of the latches employed by the circuit.
When implemented in hardware, latches included in high-performance applications generally exhibit latch transparency; a condition that allows a latch to operate properly even when data arrives at an input of the latch after a leading edge of a clock pulse that is used to launch data from the latch. Latch transparency may relax certain timing constraints of a circuit design, and should be modeled by a timing tool to provide a circuit designer greater flexibility. Unfortunately, latch transparency is not efficiently modeled using conventional timing tool techniques because such modeling is computationally expensive and a timing report created by the timing tool is difficult to interpret, for example, by a designer.
One conventional technique for modeling the behavior of a circuit in a timing tool treats each latch in the circuit as non-transparent. In a non-transparent latch (e.g., master/slave latch), data typically is captured by a first latch in the master/slave latch with a trailing edge of a capture clock signal, and is launched out of a second latch in the master/slave latch with a leading edge of a launch clock signal. Accordingly, when latch transparency is ignored, a timing tool must ensure that (1) data arrives at the first latch before a trailing edge of a capture clock signal which is used to capture data with the first latch; and (2) data arrives at the second latch before a leading edge of a launch clock signal which is used to launch data from the second latch. Although the above static timing model is easy to implement and does not require a static timing tool to perform a large amount of computation, such an approach places artificial timing constraints on a circuit design that may result in degraded circuit performance and that would not be present if latch transparency was considered. A non-optimal circuit design may result.
In another conventional technique for modeling the behavior of a circuit in a timing tool, every latch in the modeled circuit is treated as transparent. When every latch is treated as transparent, greater design flexibility is provided. However, a timing tool that treats all latches as transparent must determine the worst-case cycle time due to constraints imposed by all possible paths of a circuit design to ensure that signals reach their destinations as required by the circuit design. As such a large and in many cases unnecessary amount of computation is required to employ such a timing model.
Accordingly, additional methods for modeling latch transparency would be desirable.